The present invention relates generally to flash memory storage systems, and more specifically to such a system in which data to be written to the flash memory is scrambled to help reduce certain data pattern-dependent sensitivities and disturbance effects.
A “flash file system” provides a system of data storage and manipulation on a flash memory device that allows the device to emulate a magnetic disk. A flash file system enables applications or operating systems to interact with a flash memory device not using physical addresses but rather using logical addresses (sometimes called virtual addresses). An intermediate software layer between the software application and the physical memory system provides a mapping between logical addresses and physical addresses. Some systems that implement logical-to-physical address mapping are described in U.S. Pat. No. 5,404,485 to Ban, in U.S. Pat. No. 5,937,425 to Ban, and in U.S. Pat. No. 6,591,330 to Lasser, all three of which patents are incorporated herein by reference in their entirety.
NAND flash memories are inherently susceptible to specific data patterns. For example, programming many cells on the same bit line to the same data state, or many cells on the same word line to the same data state, may cause program disturb effects which may alter the cell charge distribution and shift one or more cells to a different data state. Such fixed repetitive data patterns are not uncommon in bit patterns frequently written to flash memories, particularly those written to certain blocks, such as control blocks, within a flash file system. Such control blocks are used by the file system, for example, to keep track of logical-to-physical address mapping information, and other information about the various data blocks. At times, programming even a few word lines to specific data states may also cause such disturb effects. These disturb effects, as well as others, are particularly problematic in memory arrays storing multiple bits per cell (i.e., MBC arrays), also known as “multiple level cell” (MLC) arrays, and these effects can cause one or more cells to generate a read error as a function of specific user data patterns. Certain program disturb effects are described in U.S. Pat. No. 7,023,739 to Chen, et al., (the '739 patent), the disclosure of which is incorporated herein by reference in its entirety.
To address this issue, techniques have been devised using system level data scrambling or randomization to eliminate the particularly problematic data patterns in the user data and control blocks before programming into a flash device. In this context, the act of scrambling or randomizing data refers to breaking up the bit patterns associated with the memory cell states along memory bit-lines and word-lines. However, such data scrambling techniques implemented outside the NAND memory are incompatible with the use of Flash Memory On-Chip-Copy or Copy-Back operations, and cannot achieve the system performance that would otherwise be attainable. Such an on-chip-copy operates on chunks of data to autonomously relocate data from one physical memory location to another physical memory location. This provides higher performance and requires less power consumption than is achievable without using on-chip copy operation, in which data is read from the device and communicated off-chip to a companion device (e.g., a flash controller device), then re-written into a different physical location of the NAND memory. However, an on-chip copy operation performed on data that is scrambled based on a physical memory address will unintentionally associate the scrambled data with a new key/seed, and results in the inability to properly descramble the data using the incorrect new key/seed to retrieve the original intended data.